Latches and flip-flops
Everything so far has been combinational: the output depends only on the inputs right now. A computer also needs memory: outputs that depend on what happened before. The trick is feedback, wiring an output back toward an input.
Feedback can misbehave
Wire a NOT gate's output to its own input. If the output is 1, the input is 1, so the output wants to be 0, so the input is 0, so the output wants to be 1... The circuit never settles. Real hardware would oscillate; the simulator marks the loop with a yellow X.
See it: the feedback loop example.
The SR latch: feedback that settles
Cross-couple two NOR gates: each gate's output feeds one input of the other. Call the free inputs S (set) and R (reset) and the outputs Q and Q-bar.
- S=1, R=0 forces Q to 1.
- S=0, R=1 forces Q to 0.
- S=0, R=0 holds whatever Q was. The loop is stable in both states, which is the whole point.
- S=1, R=1 is forbidden: both outputs go 0 and the state after release is a race.
Build it in the simulator with two NOR gates and watch what happens when you flip S on and off again: Q stays 1. That is one bit of memory, and it is roughly how a static RAM cell works (with inverters instead of NORs and a transistor to gate access).
Why clocks exist
A latch is transparent: while it is enabled, changes on the input pass straight through, and a chain of latches would let a value ripple through several stages in one go. Synchronous designs instead use a flip-flop, which samples its input only at the instant a clock signal rises from 0 to 1 (the rising edge) and holds the result until the next edge. Between edges, the input can change freely without disturbing the output. That is what lets millions of flip-flops update in lockstep once per clock cycle.
The D flip-flop
The simplest flip-flop has a data input D, a clock input CLK and an output Q. On each rising edge, Q becomes whatever D was at that moment. The simulator has a DFF gate that behaves exactly like this; add an input named CLK and press Pulse CLK to generate one clean 0-1-0 pulse.
The JK flip-flop
A JK flip-flop has two control inputs. On a clock edge:
| J | K | Q after the edge |
|---|---|---|
| 0 | 0 | unchanged (hold) |
| 1 | 0 | 1 (set) |
| 0 | 1 | 0 (reset) |
| 1 | 1 | flipped (toggle) |
The toggle mode is why JK flip-flops show up in counters: feed J=K=1 and each pulse flips the bit, dividing the clock frequency by two. You can build a JK from a D flip-flop plus a little logic: D = (J AND NOT Q) OR (NOT K AND Q). Check it against the table above: with J=K=1 it reduces to D = NOT Q, a toggle.
See it: the JK flip-flop example places the JK module. Double-click the module to open it and see the D flip-flop inside. Set J=1, K=1 and pulse CLK a few times to watch Q toggle.
What to take away
Combinational logic computes; feedback remembers; clocks keep everyone honest. With a full adder (guide 2), a mux (guide 3) and a row of flip-flops, you have the parts of a tiny CPU: a register file, an ALU and a way to step through time.