The multiplexer
A multiplexer ("mux") is a switch. It has data inputs, one select input, and one output, and it copies whichever data input the select line points at. The smallest one, a 2-to-1 mux, has inputs A and B and a selector S:
| S | Y |
|---|---|
| 0 | A |
| 1 | B |
As a formula: Y = (A AND NOT S) OR (B AND S). Read it as two gated lanes. The left AND lets A through only while S is 0; the right AND lets B through only while S is 1; the OR merges the lanes, and since exactly one lane is open at a time there is never a conflict.
Build it
- Place inputs S, A and B and an output Y.
- NOT S gives the "lane 0 open" signal.
- AND(A, NOT S) and AND(B, S) are the two lanes.
- OR the lanes into Y.
Four gates. Flip S in the simulator and watch Y follow A, then B.
Try it: Practice puzzle 5, "The Switchboard".
The NAND version
Because OR of two ANDs is the same as NAND of two NANDs (De Morgan again), the mux collapses nicely onto NAND gates: Y = NAND(NAND(A, NOT S), NAND(B, S)), with NOT S = NAND(S, S). Still four gates, and this is close to how a real CMOS mux cell is laid out.
Where muxes hide
- Memory. Reading address 5 out of 256 cells is a 256-to-1 mux built as a tree of 2-to-1 muxes with eight select bits.
- Processors. Every "if" in hardware is a mux: compute both answers, then select one. The ALU picks between add, subtract, AND and OR results with a mux driven by the instruction.
- FPGAs. A programmable logic block is mostly a small memory feeding a mux. Any function of a few inputs can be stored as a table and looked up.
- Everyday things. HDMI switches, audio source selectors and the "input" button on a monitor all do the same job at different speeds.
A mux can be anything
Here is a party trick: a 2-to-1 mux is itself universal. Wire A and B to constant 0 and 1 in different combinations and you get NOT, AND and OR. That is exactly why FPGAs use them as building blocks. In Gatesmith puzzles you have no constant inputs, which is why NAND or NOR stays the usual "only one gate" challenge.